Signal Layer Checks



Signal Layer Checks


Open Signal Layer Checks


Parameters

Parameters:

Layer

Spacing

Rout to Cu

Drill to Cu

Sliver min

Minimum pad overlap

Test list

Apply to

All Analyze all features in the layer
Selected Analyze selected feature

Check Missing Pads for Drills

Use Compensated Rout

Sort Spacing by Solder Mask


Set Range

Range:

Spacing

Spacing explained:

Circuit includes the following features: Line, Pad, Surface, Arc

Example:To analyze spacing distance for Arc to Circuit, there is no such option, however, since arc is included in the circuit category, Circuit to Circuit can be used to analyze results for Arc to Circuit

Pad to Pad

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Pad to Circuit

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SMD to Circuit

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BGA to Circuit

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Circuit to Circuit

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Line to Line

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Circuit to Line

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Text to Text

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Spacing Length

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Same Net Spacing

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Toeprint to Toeprint

SMD to SMD

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SMD to Pad

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BGA to BGA

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BGA to Pad

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Via(Pad) to Via(Pad)

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PTH(Pad) to PTH(Pad)

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Exposed to Exposed

Covered to Covered

Exposed to Covered

Exposed to Fully Covered


Drill

NPTH to Pad

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NPTH to Circuit

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PTH to Copper

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PTH to Line

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PTH to Pad

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Via to Copper

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Via to Line

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Via to Pad

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PTH Annular Ring

In Advance parameter setting:Set Classify pad annular ring to no - Check annular ring distance for PTH/Via holes

In Advance parameter setting:Set Classify pad annular ring to yes - Check annular ring distance for PTH (Comp) Annular Ring and Via Annular Ring separately

PTH (Comp) Annular Ring

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Via Annular Ring

In Advance parameter setting:Se Classify via annular ring to no Check annular ring distance for all Via holes

In Advance parameter setting:Classify via annular ring = yes - Check annular ring distance for Via Annular Ring 、 Laser Via Annular Ring and Photo Via Annular Ring separately

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Laser Via Annular Ring

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Photo Via Annular Ring

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NPTH Annular Ring

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PTH Registration

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  1. Distance value higher than Reg_Allowance ERF。

  2. Distance value lower than Max_Reg ERF。

NPTH Registration

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  1. Distance value higher than Reg_Allowance ERF。

  2. Distance value lower than Max_Reg ERF。

Missing Pad for Via

Missing Pad for PTH

Missing Cu for Via

NPTH touches Copper


Rout

Rout to Copper

Missing Cu for Plated Rout


Size

Pads

Lines

Rotated lines

Shaved lines

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Inconsistent Line Width

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Arcs

Shaved Arcs

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Inconsistent Arc Width

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Line Neckdown

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Text

Text Fields


Sliver

Slivers

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Local Spacing


Stub

Stubs

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SMD

SMD Pitch

SMD Pads

Shaved SMD

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SMD Packages

BGA Pitch

BGA Pads

Shaved BGA

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BGA Packages


Bottleneck

Conductor width

Detect line width lower than Max bottleneck width value

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Other

Plated Rout Annular ring

incoming Trace to Hole

Net Too Large

Ignored Net

Pad to Pad Connection

Pad to Cu Connection

Pad to Line Connection

feature too small to check


Set Advance Variables

Advance Variables:

General

Report line with arcs

Use Spacing parameter as Tolerance of Checked Area

Tolerance of Checked Area

Drill

Classify pad annular ring

Yes Classify annular ring by drill hole type (.drill=plated => PTH (Comp) Annular Ring, .drill=via => Via Annular Ring)
No All annular ring are regarded as PTH Annular Ring

Classify via annular ring

Yes Classify annular ring by via hole type(e.g. .via_type= laser => Laser via Annular Ring)
No Via Annular Rings not classified by via hole types

Reg Allowance

Max Reg


Spacing

Classify pad via to circuit

Yes Classify via hole based on via hole types (e.g. .via_type= laser => Laser vai Annular Ring)
No Ignore via hole types

Classify pad SMD to circuit

Yes Classify standard pad and SMD pad (e.g. SMD pad to Circuit, Pad to Circuit)
No Ignore Pad types, use Pad to Circuit for all pads

Classify pad BGA to circuit

Yes Classify standard pad and BGA pad (e.g. BGA to Circuit,Pad to Circuit)
No Ignore Pad types, use Pad to Circuit for all pads

Classify pad to pad

Yes If one of the pad has .toep_spacing_req attribute, use Toeprint to Toeprint
Yes If both pads are SMD or BGA pads,use SMD to SMD or BGA to BGA
Yes If only one of the pad is SMD or BGA,use SMD/BGA to Pad
Yes If one of the pad is drilled by PTH holes,use PTH to Pad
Yes If one of the pad is drilled by Via holes,use Via to Pad
No Ignore Pad types, use Pad to Pad for all pads

Classify circuit to circuit

Yes Classify based on feature type: Line to Line,Circuit to Line,Circuit to Circuit
No Ignore feature types, use Circuit to Circuit only

Self spacing

Select Net type

Layer Net Only analysis net on the current layer
Boad Net Reference all net in board layers

Spacing length measure


SMD

Max SMD

Pitch tolerance


BGA

Max BGA

Pitch tolerance


Rout

Check plated rout to copper

Plated rout min annular ring


Sliver

Min Sliver length

Length to sliver width ratio

Stub

Max surface stub width

Min surface stub length


Size

Min line length

Max line width

length to width ratio


Bottleneck

Max bottleneck width

Length to bottleneck ratio

ignore text

Yes Include text features in Ignore net
No Ignore text(Sliver)

Other

Ignored attributes

Large net min

Use multiple threads

Yes Turn on Multithreading
No Turn off Multithreading

Run Signal Layer Checks


View Analysis Report


Result Viewer Form

Result Viewer Form Introduction

:Display analysis result by selected layers

:

:Number of detected error types

:Back to the first error entry

:View previous error entry

:View next error entry

:Jump to the last error entry

:Error entry index number

:Choose method to view error entry in the layout:

:Remove reference mark

:Add reference mark

:Remove error entry marked with reference mark

:Open Result Report

:Open Result Histogram

:Error entry severity levels, red color is the most critical errors

:Display all error area in the layout

View Detected Error in the Layout

View Result Histogram for Analysis

Command:chklist_ hist_close

Command:chklist_ hist_show